Challenges for interconnect of future CMOS generations : Implementation of emerging processes and alternative architectures

The paper points out several challenges that interconnects fabrication are facing for next technology nodes in terms of integration of porous low-k dielectric and advanced metallization. These new processes are required in order to meet RC performances but also need to reach desirable reliability aspects. k value degradation of low-k during integration is discussed as well as copper resistivity increase in narrow lines. Process solutions to relax these issues are developed. Finally alternatives architectures, such as air gap isolation, are introduced and proposed as solutions that may be implemented in order to extend the end of roadmap of conventional metal interconnect of CMOS technologies.