Process development and reliability for wafer-level 3D IC integration using micro-bump/adhesive hybrid bonding and via-last TSVs

Wafer-level hybrid bonding and through silicon vias (TSVs) are key technologies to fabricate 3D IC products with ultra-fine pitch bumps and high interconnects density. In this work, process optimization and reliability evaluation of 3D IC integration using wafer-level micro-bump/dry film adhesive hybrid bonding and via-last TSVs were presented. In order to obtain a well hybrid bonding interface, various hybrid bonding methods, i.e., low temperature bonding using no reflowed bump, high temperature bonding using no reflowed bump, and high temperature bonding using reflowed bump, were investigated. Key processes including dry film lamination, hybrid bonding, and via-last TSV fabrication were developed. Reliability of the hybrid bonded chips were characterized by various tests. The results indicate that wafer-level hybrid bonding with via-last TSVs approach is a reliable, simple solution to fabricate 3D IC products.