1.5µm scaled CMOS microcomputer technology
1984
This paper will discuss the application of 1.5μm CMOS technology by integrating existing NMOS devices with an N-well CMOS approach. Bulk P- substrates were replaced with Pepi on P+ substrates for reduced latchup susceptability. Minimum gate delays of 190ps and a 36% linear shrinkage of an 8b microcomputer have been realized.
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