A system to optimize inline defect detection using short loop testchips leading to faster yield learning

With every new manufacturing node also come new modes of failures. Being able to identify these new fail modes and solve them quickly is the key to bring a manufacturing process to mass production readiness. Inline inspection is typically used for studying defects at critical layers. However, this is often limited by the amount of defects that can be visually inspected and to be able to qualify them between killer and false defects. We describe a powerful methodology combining electrical measurements from CV® testchips and inline inspection to make efficient usage of limited inline inspection resources and be able to identify new defect types that will eventually cause yield loss. This methodology can also be used to optimize inline inspection recipes and apply to production wafers.