A 7.39mm 2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications

This paper presents the LDPC decoder chip for (1944,972) QC-LDPC codes in IEEE 802.11n communication system. The efficient LDPC decoder chip is designed with three design techniques, including Group Comparison (GC), Dynamic Wordlength Assignment (DWA), and Data Packet Scheme (DPS). When the target BER is 10 -6 , the decoding performance can be improved by the coding gain of 0.48 dB and 0.63 dB with respect to (4,3) and (3,2) fixed-point NMSA, respectively. In addition, the total decoder design area can be reduced by 25% and the decoding throughput can be enhanced by 3X times with respect to conventional direct-mapping method. By using TSMC 0.13 um VLSI technology, the core area and die size are only 3.88 mm 2 and 7.39 mm 2 , respectively. The maximum operating frequency is measured at 111.1 MHz and the power dissipation is only 76 mW.