A System Function Verification Flow For Mixed-signal SoC

Taking a mixed-signal SoC project as an example, this article introduces an efficient system function verification flow applied to mixed-signal SoC. All the inherited analog IPs in this project are developed in virtuoso environment, and the digital modules are simulated in VCS environment. The system function verification platform of this project uses UVM(Universal Verification Methodology) to generate digital stimulus and Verilog-AMS to generate analog stimulus. The overall circuit is transformed into spectre-netlist and integrated into the verification platform. The project has high requirements on the development and simulation progress. The system function verification is realized by using simulation tools VCS and XA of Synopsys. The results of the project are correct, which shows the effectiveness of the flow.