CMOS Image Sensor Data-Readout Method for Convolutional Operations with Processing Near Sensor Architecture

In this paper, we propose a CMOS image sensor data-readout method for convolutional operations based on 3T-APS pixel, which is able to output convolutional kernel-sized data from sensor parts simultaneously, with processing near sensor architecture. By adding extra output lines in the pixel array and introducing a digital controlled analog crossbar named programmable analog tunnel hub (PATH), the proposed CIS can realize maximum 5X5 kernel-readout with minimum 1 slide step. The proposed CIS readout method has been verified by pixel array with 32X32 resolution, where each pixel occupying 40X40 m 2 area with 83.6% fill factor. The CIS is designed in 180nm standard CMOS mixed-signal process with power consumption of 5.66mW and frame rate of 100fps@20MHz. Compared with previous vision sensor chips, this work is optimized for prevailing deep learning applications and achieves higher energy efficiency for the whole smart perception systems with better scalability.