Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure

Abstract The impact of random dopant fluctuation (RDF) on a 10-nm n-type silicon (Si) FinFET with a metal-insulator-semiconductor (M-I-S) source/drain (S/D) structure is investigated using three-dimensional TCAD simulation. To determine the optimal aspect ratio of the fin for a variation-robust FinFET with an M-I-S S/D structure, various metrics for device performance are quantitatively evaluated. It is found that variation in RDF-induced threshold voltage ( V th ) in the FinFET can be suppressed with a taller fin (i.e., a fin with a higher aspect ratio) because of better gate-to-channel controllability and wider channel width. For a fin aspect ratio (i.e., fin height to fin width) of 5.25:1, the standard deviation for RDF-induced V th in a FinFET with an S/D doping concentration ( N S/D ) of 5 × 10 20  cm −3 is 9.277 mV. In order to suppress RDF-induced V th variation even further, an M-I-S structure with a heavily doped n-type ZnO interlayer can be introduced into the S/D region of the FinFET. For the tallest fin height, this M-I-S S/D structure (with an N S/D  = 5 × 10 19  cm −3 ) results in a standard deviation of 4.729 mV for RDF-induced V th , while maintaining the on-state drive current ( I on ) at a satisfactory level. Therefore, it is expected that a 10-nm n-type FinFET can be designed to be immune to V th variation with the adoption of the proposed M-I-S S/D structure.