Static random access memory unit resisting single event upset

The invention discloses a static random access memory unit resisting single event upset. The static random memory unit resisting the single event upset comprises a first differential series voltage switch logic unit, a second differential series voltage switch logic unit, a first PMOS (P-channel Metal Oxide Semiconductor) transistor resistor, a second PMOS transistor resistor, a first access NMOS (N-channel Metal Oxide Semiconductor) transistor and a second access NMOS transistor, wherein the first access NMOS transistor is connected with the first differential series voltage switch logic unit, the second access NMOS transistor is connected with the second differential series voltage switch logic unit, the first PMOS transistor resistor and the second PMOS transistor resistor are connected between the first differential series voltage switch logic unit and the second differential series voltage switch logic unit in parallel, and the first differential series voltage switch logic unit and the second differential series voltage switch logic unit constitute a cross-coupling latch.