A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65nm CMOS

This paper presents an 8-channel energy-efficient analog front-end (AFE) for neural recording, with improvements in power supply rejection ratio (PSRR) and dynamic range. The input stage in the low noise amplifier (LNA) adopts low voltage supply (0.35 V) and current-reusing to achieve ultra-low power. To maintain a high PSRR performance while using such a low-voltage supply, we propose a replica-biasing scheme to generate a stable bias current for the input stage of the LNA despite large supply interference. An averaged local field potential (A-LFP) servo loop is introduced to extend the dynamic range without consuming too much extra power and chip area. The A-LFP signal is generated by integrating from four-channel PGA outputs. Furthermore, the outputs of the programmable gain amplifier (PGA) are level shifted to bias the input nodes of the amplifier through large pseudo resistors, thus increases the maximum output range without distortion under the low-voltage supply. The proof-of-concept prototype is fabricated in a 65 nm CMOS process. Each recording channel occupies 0.04 mm 2 and consumes 340 nW from the 0.35 V and 0.7 V supply. The maximum gain of the AFE is 54 dB, and the input-referred noise is 6.7 μV over the passband from 0.5 Hz to 6.5 kHz. Measurement also shows that the 0.35 V replica-biasing input stage can tolerate a large interferer up to 200 mVpp with a PSRR of 74 dB, which has been improved to 110 dB with a silicon respin that shields critical wires in the layout.