A Low Power High Precision Burst-Mode CMOS Clock Recovery Circuit for 28.8 Mb/s Passive Optical Network

We report on a 15 mW clock recovery circuit with instantaneous locking for a 28.8 Mb/S Passive Optical Network. The actual range of operating data rates of this chip fabricated in standard digital 0.9 ?m CMOS is 25 - 130 Mb/s. Based on a previously proposed scheme, this circuit can handle data with even lower transition densities than proven earlier. At 28.8 Mb/s, 120-bit strings of only "ones" or only "zeros" are processed with better than 10 ?10 error rate. The circuit architecture includes an intentional factor-of-two reduction in its capability to accept long strings of bits without transitions, traded for excellent immunity to input data duty cycle variations. Phase jitter and not device matching limited the precision of the current implementation.