Enabling a Robust Copper Seed Etch Process for Fine Line RDL by Electroplating on a Thin PVD Seed Layer

Abstract Integration of heterogeneous chips into fanout packages requires interconnection by redistribution lines (RDL). As I/O counts increase, higher density routing is required, and can be achieved by finer RDL line/space dimension, stacking multiple RDL layers, or both. Conventional WLP plating processes for pillar or RDL use a PVD deposited copper seed layer between 1000 and 4000A thick. Removal of this copper seed layer by isotropic wet etching leads to sidewall loss that can be ignored on larger features, but can lead to significant copper cross sectional area loss on features with 2/2μm line/space and below. By enabling plating onto much thinner seed layers, next generation WLP plating chambers enable a conventional copper seed layer etch process with less sidewall loss and more uniform cross-sectional area across plated features.