Design and initial characterization of MIC4, the monolithic active pixel sensor prototype for CEPC vertex detector

Abstract The Circular Electron Positron Collider (CEPC) is proposed as a Higgs factory to produce adequate events, which are the basis for high-precision measurements of the Higgs boson. The vertex detector in the CEPC should meet the requirements of a low material budget, high spatial resolution, fast readout speed and low power consumption. A monolithic active pixel sensor (MAPS) has been selected as the most promising technology for the vertex detector. The MIC4 sensor is the first prototype developed within the preliminary R&D activities of the CEPC vertex detector. It has been implemented in the TowerJazz 180 nm CMOS image sensor (CIS) process. It measures 3.1 mm × 4.6 mm and features a 128 row × 64 column pixel array with a pixel pitch of 25 μ m . In this work, a binary front-end has been designed for a compact pixel combined with a sparsified readout circuitry. Each pixel is composed of an amplifier, a shaper, a discriminator and digital logic. A new asynchronous zero-suppression data-driven readout circuit architecture is proposed and implemented in MIC4. We have performed some initial tests on this chip and obtained detailed results. The front-end features a peaking time below 1 μ s , a shaping time less than 3 μ s , a charge threshold of approximately 100 e − , an average temporal noise (TN) of 6 e − and a fixed pattern noise (FPN) of 36 e − . The addresses of the fired pixels can be readout in the digital part of the chip at a clock running at 30 MHz with the new data-driven readout circuit architecture. The hit map under 55Fe X-ray exposure shows that the sensor designed in MIC4 works well. The probability of single event latch-up (SEL) σ SEL is 1.02 × 10−6 cm2 at a linear energy transfer (LET) of 20.05 MeV cm2/mg.