On the Connection of SRAM Cell Stability with Switching History in Partially Depleted SOI Technology

Read and write operational margins for SRAM cells in partially depleted silicon on insulator (PD-SOI) technology are studied. In both simulation and concept, cell stability is shown to be directly connected to the inverter nFET first switch/second switch history, thus linking SRAM margins to a PD SOI parameter that can be measured and monitored