An Efficient 64-Point IFFT Hardware Module Design

This paper presents the process of designing a 64-point IFFT hardware module, as a 2D structure of 8-point IFFT pipeline modules. The proposed 64-point IFFT module utilizes only two 8-point IFFT modules, which include minimal number of multiplications and additions, and as well provides parallel processing of eight symbols in each pipeline phase. This allows high throughput performances of the proposed 64-point IFFT module and chip area savings of its hardware implementation on Virtex 5 FPGA. The realized hardware design can be easily applied in a high-speed real-time system, such as OFDM-based communication system.