Utilizing a Thorough Understanding of Critical Aging and Failure Mechanisms in finFET Technologies to Enable Reliable High Performance Circuits.

In order to design competitive circuits in finFET technologies, a designer must intelligently navigate the plethora of reliability rules, As an example, by understanding the trade-offs between transistor self-heating, Joule-heating due to Irms currents and passing Iavg rules at higher temperatures, designers can optimize the design changes required to meet overall interconnect reliability requirements. In addition, accounting for appropriate levels of Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI) aging during timing closure requires knowledge of the critical path behavior and interactions. Furthermore, voltage limits based on time-dependent-dielectric breakdown (TDDB) for gate-dielectrics can be tailored based on total area exposed to a given voltage. A Design-for-Reliability (DFR) methodology is presented, which prevents over-design by accounting for accurate mission-mode operation, and enables improvements in performance, and reduction of area, along with Si-based validation of robustness with respect to aging.