LSI/VLSI Ion Implanted Planar GaAs IC Processing

Abstract : The scope of this program is to complete and stabilize the development of a planar fabrication process for high speed digital integrated circuits on 3-in. GaAs wafers. In the six-month period covered by this was made in the areas of materials characterization, uniformity evaluation, and gate array design. Annealing experiments were performed on as-grown GaAS wafers to evaluate methods of damage gettering to reduce the metal concentration in active layers and to improve the reproducibility of the implant process. The results were somewhat inconsistent because of unusually high manganese levels in the ingot. To help determine those factors which influence threshold voltage variation, a simple C-V technique was established. One feature illustrated by the C-V data is that most reported nonuniformities in the LEC material which has been reported is due to systematic rather than random variations in threshold voltages. The statistical variation in threshold are generally much smaller being on the order of 20 mV. Standard deviations due to the larger systematic variations have been typically 50-70 mV. The AR8 mask set is in the second phase of the on-going gate array development program. The masking plates for fabricating the generic underlayers have been received in-house, and Mayo had completed the customization layers. The UCSB circuits have been placed on the mask. The customization layers are ready to be sent to the mask shop.