A numerical analysis of the storage times of dynamic random-access memory cells incorporating ultrathin dielectrics

A numerical simulation of the dynamic random-access memory (DRAM) cell which incorporates leakage currents through the capacitor is presented. As a DRAM cell capacitor dielectric is made thinner, the storage time becomes longer; but at some thickness, leakage currents through the dielectric will become significant, and further reductions in thickness will shorten storage time. The dominant leakage mechanism for a capacitor with thin SiO/sub 2/ as an insulator is direct tunneling. For Si/sub 3/N/sub 4/, even moderate thicknesses exhibit the low-field hopping and the high-field Poole-Frenkel conduction. The simulation shows that the dielectric thickness that provides the maximum storage time at a given elevated temperature exhibits significant leakage at room temperature, but the maximum storage time can be achieved as long as the high-temperature junction leakage is larger than the dielectric leakage. The maximum storage time values are obtained with an SiO/sub 2/ thickness of about 3.8 nm or a Si/sub 3/N/sub 4/ thickness of about 3.5 nm.