A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput

Hiroki Nakamura,Keniti Imamiya,Toshihiko Himeno,Toshio Yamamura,Tamio Ikehashi,Ken Takeuchi,Kazushige Kanda,Koji Hosono,Takuya Futatsuyama,Koichi Kawai,Riichiro Shirota,N. Arai,Fumitaka Arai,Kazuo Hatakeyama,Hiroaki Hazama,M. Saito,H. Meguro,K Conley,Khandker N. Quader,Jian Chen

A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput

2002

A 125 mm/sup 2/ 1Gb NAND flash uses 0.13 /spl mu/m CMOS. The cell is 0.077 /spl mu/m/sup 2/. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

Keywords:

Parallel computing
Computer science
Garbage collection
NAND gate
CMOS
Memory architecture
Architecture
Chip
Throughput
Flash memory
Computer hardware
nand flash memory
Embedded system
Voltage
Decoding methods
Electronic circuit

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