First SOI Tunnel FETs with low-temperature process

We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage (V TH ) of p-mode operating TFETs shows a 300 mV reduction with similar ON state currents (wrt HT reference), opening path towards optimized devices (very low V TH & supply voltage V DD )