Self-aligned process for producing a double gate MOSFET

The invention describes a self-aligning method of manufacturing a double gate transistor. The component areas (3B: source / drain, 3C: Channel) can be prepared in the first step by selective, lateral undercutting of an insulating layer and a buried first formed selectively etchable layer in a layered structure. The two selectively etchable layers are then etched back from the side so that tunnels (T1, T2) on and under the channel (3C) are formed. These are after formation of the gate dielectrics (7) filled up on the semiconductor layer with an electrically conductive gate material. The upper and lower gate (8) are characterized both to each other and to the source and drain regions (3B) perfectly adjusted.