Analysis of field-plate LDMOS devices for RF applications

One of the design difficulties found in SJ power RF LDMOS transistors is the P/N pillars doping inter- diffusion which increases with the lateral diffusion factor and degrades the device RON-sp. An alternative 3-D RESURF method consists on placing a trench oxide of predetermined thickness together with a grounded polysilicon layer inside the trench along the LDD region to replace the P pillar of the SJ LDMOS. The metal-thick-oxide block acts as a field-plate (FP), enhancing the 3-D RESURF lateral depletion which allows increasing the N-drift doping concentration. In order to study the feasibility of applying the FP concept in RF LDMOS transistors a preliminary analysis has been performed to compare the performance of SJ LDMOS with the proposed FP LDMOS structure in terms of drift region resistance (RLDD), voltage capability (VBR) and transconductance (gm) by means of theoretical analysis and extensive 2-D numerical simulations.