A New Allocation Method for the Synthesis of Partitioned Busses

The allocation task in high level synthesis systems maps operations of a behavioural description to functional units and determines the number of registers, multiplexers and wires. Although the number of multiplexers and wires is minimized, a rather large amount of space is used for the individual connections between the functional units. We reduce this space drastically by generating partitioned busses. For this purpose a parameterized and powerful bus architecture is defined. A method which partitions a data flow graph to allow a bus oriented design and a new allocation method are presented in this paper. First experiments with this approach were successful and lead to very small designs.