Signal and Power Integrity Analysis of InFO Interconnect for Networking Application

MediaTek INFO Link (M-Link) is worldwide first successful homogeneous DIE-to-DIE data link for high-speed networking application. Considering benefits from large on-die capacitance of core-power domain, merged power domain for INFO and core-power is adopted. However, in order to sustain over 250W external core-power interference and internal INFO SSO noises, optimization of whole band target impedances to against these noises becomes one of major challenges. In this paper, a systematic approach to design M-Link in the extreme condition is proposed. In first part of paper, modulated chip power model (MCPM) technology is applied to ensure System-PDN. MCPM is modulated CPM which serves as new current load to represent mid-frequency bands interference for system level time domain noise simulations. In the second part, input pattern modulation (IPM) was applied to predict worst power ripple on INFO I/Os and jitter from sensitive circuit critical path. The IPM methodology serves as a total assessment considering all SI/PI impact to ensure a robust design. Finally, given fully consideration on System-PDN and INFO SI/PI, INFO I/Os with 4.8Gbps speed achieved 70% ETT eye windows in both simulation and verification. The design trade-off on core-power merged and separated is also discussed for future higher system bandwidth requirement.