Matrix multiplication by an inexact systolic array

Different schemes for approximate computing of matrix multiplication (MM) in systolic arrays are presented in this manuscript. Inexact full adder cells are utilized in a processing element (PE) for the Baugh-Wooley multiplier and/or the final adder as circuits implementing the two computational steps required for MM. An extensive analysis and simulation-based assessment of three inexact schemes for the PE are pursued with respect to circuit level performance (such as delay, power consumption and number of transistors) and figures of merit of approximate computing (such as the error distance). The execution of MM in each PE results in an inexact computation affecting only the outputs of the same columns, so the extension of inexact computation to a systolic array can also be performed with very limited error. The discrete cosine transform as application of the proposed inexact systolic arrays, is evaluated; simulation results show that the proposed inexact array is very effective, incurring in a small error.