A 15-ns 32*32-b CMOS multiplier with an improved parallel structure

A high-speed 32*32-b parallel multiplier with an improved parallel structure using 0.8- mu m CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-*2.71-mm/sup 2/ die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved. >