A 13 bit 20 Ms/s current mode pipelined analog to digital converter

A pipelined analog to digital converter based on open loop differential CMOS switched current amplifiers is presented. It is hard to meet the requirements of opamps for conventional switched capacitor ADCs at low power applications. For high accuracy, closed loop amplifiers also require high quality double poly capacitors for good matching which are not otherwise required in a digital CMOS process. The proposed technique can achieve high speed and high accuracy at low voltage supplies with relatively low power and it does not require good device matching. This makes it suitable to be integrated in a low cost digital CMOS process. Analog or digital calibration and trimming are not required-dynamic autocalibration is used. The challenges and proposed solutions are described and a 13 bit (12 bit linearity) 20 Msamples/s test chip which has been fabricated with a 0.6 /spl mu/m CMOS process with the proposed techniques is presented.