Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs

Testability analysis in the RTL design cycle of an IP or SoC is a critical need for designers to minimize design iterations and resources, and to enable faster design closure times. A mandatory requirement for any such technique is its scalability and applicability to large and complex industrial designs. In this paper, we share an RTL testability analysis framework developed to address the above need. The framework consists of three main components: (i) A strong static design rules for testability checker that can audit an RTL circuit for DFT readiness from both stuck-at and transition fault testing perspectives, (ii) Coverage estimator that can provide early bounds for achievable coverage and help pinpoint design artifacts that limit coverage, and (iii) A random pattern based analysis engine to identify hard-to-test nodes that warrant further fixes. This framework has been commercially used by multiple customers. In collaboration with one of our customers, we share empirical data from applying this methodology to various IPs in a recently taped-out 45nm SoC.