A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]
2001
A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns asynchronous page mode access and synchronous burst reads up to 100 MHz with zero wait state.
Keywords:
- Conventional memory
- Electronic engineering
- Parallel computing
- Computer memory
- Bubble memory
- Registered memory
- Computer science
- Racetrack memory
- Non-volatile random-access memory
- Dynamic random-access memory
- Computer hardware
- Flash memory
- Flash file system
- Memory refresh
- Electrical engineering
- Sense amplifier
- Memory architecture
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
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