Design Optimization of High Density Fine Line Substrate Package Using Bandwidth Analysis

To satisfy the demand of high bandwidth of chip-to-chip communication, it is essential for high performance computing (HPC) chip with heterogeneous integration package to utilize fine lines. This paper presents the electrical performance and optimal bandwidth design flow on embedded organic substrate fine lines. Due to their feature of thin copper traces, fine lines behave as highly lossy transmission lines. This optimal bandwidth design flow is based on eye diagram simulation results to create the bandwidth contour map for design reference. This map can provide designers a whole-picture reference if there is a tradeoff between circuit performance and process capability. The optimal bandwidth results of advanced 1/1, 2/2 and 3/3μm of line width and spacing among four channel designs are also demonstrated in this work.