High-performance CMOS clock distribution

In this chapter, we provided background on three major jitter sources in high performance CMOS clock distribution: power supply induced jitter (PSIJ), random jitter (RJ), and jitter amplification. We discussed how PSIJ is introduced in the CMOS inverter and its accumulation along a chain of buffers depending on the type of supply noise and its variation along the buffer chain. We also reviewed the analysis of RJ in the CMOS inverter. We described design tradeoffs to minimize both PSIJ and RJ in global clock distribution. We described linear models of jitter amplification, including the jitter impulse response (JIR) and jitter transfer function (JTF). Jitter amplification for buffers driving transmission -line interconnect was analyzed quantitatively, and simulations were used to develop insight. Design guidelines are also given for both cases. Finally, we discussed design considerations for jitter amplification in CMOS clock distribution. With the increasing use of CMOS circuits for high-performance clock distribution in advanced CMOS technologies, we believe the methods and guidelines in this chapter will prove ever more useful.