Thickness dependence of low-level leakages in thin oxides

The wearout of 4 nm to 13 nm thick oxides fabricated on n-type and p-type substrates was measured. The interface trap densities, flatband voltage shifts, bulk trap densities and low-level leakage currents were measured before and after high-voltage stressing. In oxides that had been stressed at the equivalent electric fields for constant times, the measured flatband voltage shifts, interface trap densities, and bulk trap densities dropped as the oxide thicknesses dropped and were negligible for oxides thinner than 6 nm, while the low-level pre-tunneling leakage currents increased. Both an AC and a DC component to the stress-induced low-level leakages were measured. The DC component to this leakage current increased as the oxide thicknesses decreased. A model based on uniform trap generation throughout the oxide during the high-voltage stresses and tunnel charge/discharge of the traps within approximately 3 nm of either interface after the stresses were removed, has been used to explain and accurately fit all of the thickness dependences of the trap generation and leakage current measurements. The thickness dependent leakage currents will limit oxides to thicknesses greater than about 10 nm for non-volatile memory applications.