Counter circuit and frequency divider stage

Counter circuit, consisting of a chain (17) of dynamic frequency divider stages (13) each for halving the frequency of an input signal of the respective frequency divider stage (13), each frequency divider stage (13) has an input for supplying a clock signal to regenerate this stage, characterized that the chain in sub-chains (14) of predetermined length is divided, the respective first frequency divider stage (13) the clock signal can be supplied separately.