Challenges for high-density 16Gb ReRAM with 27nm technology
2015
Enabling a high-density ReRAM product requires: developing a cell that meets a stringent bit error rate, BER, at low program current, integrating the cell without material damage, and providing a high-drive selector at scaled nodes. We discuss ReRAM performance under these constraints and present a 16Gb, 27nm ReRAM capable of 10 5 cycles with BER −5 .
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