A low-overhead FFT design with higher SEU resilience implemented on FPGA

For area and power constraint applications in mission critical systems, the traditional fast Fourier transform (FFT) design requires huge hardware resources for data processing. In this article, we, therefore, present a low-overhead radix-2 FFT design that reduces hardware resources by simplifying the first two stages of the butterfly computations. Both the proposed design and the traditional design have been implemented in the MicroZus-20 (XC7Z020) platform. Their single-event performances have been compared through both fault injections and neutron exposure, and the experimental results demonstrate that the proposed design reduces the soft error rate by 53.8%. Also, the proposed FFT reduces the hardware resource consumption and circuit area by 64.8% when compared with the traditional design.