A VLSI implementation study of a 10 Mbit/s video decoder

Abstract The paper presents the study of a VLSI implementation of a video decoder, targeted for systems with bit-rates up to 10 Mbit/s. Among the features of the decoder are a CCIR 601 4:2:2 full resolution output, the regeneration of a motion compensated prediction using both spatial and temporal interpolation techniques, and an inverse DCT of the coefficients. The paper describes the algorithm of picture encoding that was implemented, gives a global evaluation of the encoding system and presents a detailed proposal for a VLSI implementation of the decoding system.