On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA

Three-dimensional Field Programmable Gate Arrays (3D FPGAs) represent a viable alternative to overcome challenges of integration complexity in modern embedded systems. Mapping applications into 3D FPGAs requires a set of accompanying suite of Computer-Aided Design (CAD) tools. One of critical issue of a 3D FPGA-based implementation is the quality and efficiency of associated CAD algorithms. In this paper, we are interested to investigate placement algorithms aspect to optimize proposed 3D FPGA performances. In fact, the way we distribute clusters between 3D FPGA layers has an important impact on performances. We present partitioning- based placement algorithm for 3D FPGA. The circuit is first divided into two layers with limited number of inter-layer interconnections, and then placed on individual layers. Placement solution of each layer is then gradually improved using adapted simulated annealing algorithm. We conduct experiments using exploration platform to compare partitioning-based and simulated annealing based placement approaches for proposed 3D FPGA architecture. Exploration results show that using partitioning-based placement algorithm achieves a saving in terms of power consumption, area and performance by an average of 15%, 18% and 10% Unlike DFPGA, MS-FPGA can deal with complex circuits.