40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU

A 160 kb SRAM macro with stable operation under widely various temperatures of -40 to 170°C is implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. We finely optimized MOS sizes of the 6T SRAM bitcell with process tuning to enhance the read margin and to reduce leakage power at high temperatures over 125°C. The optimized bitcell improves the static-noise-margin by 40 mV and reduces leakage power to 1/10 of the conventional value. To achieve high quality, we propose rush current suppression circuit when resuming from sleep-mode and a weak-bit test screening circuit. A designed test chip showed a measured V min mean of 0.65 V at 170°C and 1.86 μW/Mb (643 μW/Mb) at 25°C (170°C) with good distribution. Those are the lowest power values reported to date in published works. The estimated leakage power of a prototype MCU chip is acceptable for automotive target specifications.