A 9.7 mW 0.13 µm CMOS PLL for use in wireless sensor nodes

This paper introduces a novel low-power, high precision phase-locked loop (PLL) for use in wireless sensor nodes. These sensor nodes work in 24 GHz ISM (Industrial Scientific and Medical) frequency range and addresses several use cases and are able to improve the processes for production scheduling, logistics, quality management and medical applications. The basic structure of the sensor node and its possible applications are presented. A synthesizer structure suitable for high performance indoor localization is explained. The PLL design was manufactured with a 3 GHz test-VCO in a 0.13 µm IBM CMOS process with a supply voltage of 1.5V. It consumes a total power of about 9.7 mW (without VCO), achieves a phase noise better than 78 dBc/Hz @ 100kHz and the total structure including the ΔΣ- Modulator block with SPI (Serial Peripheral Interface) - connection consumes a silicon area of 0.09 mm 2 .