Full-chip process window aware OPC capability assessment

In the past technology generations, Optical Proximity Correction (OPC) has been applied using a model capturing the Optical proximity effects in a single focal plane. In the newer generations, this method is more and more difficult to maintain because of very small process windows in specific situations. These specific situations include 1D configurations (e.g. isolated small lines) but increasingly complex 2D configurations. In the more advanced technology nodes 2D configuration are starting to play a much bigger role. Process windows need to be preserved in all cases, and so this brings about another challenge for the OPC flow. The more traditional OPC approaches may result in un-acceptable small process window in such cases, whereas well characterized Process Window aware OPC (PW-OPC) can provide better results, with much less engineering interventions. In this paper the method of Process Window aware OPC is applied on special designed test structures and on a larger scale (full chip). Verifications and assessments are demonstrated and compared with alternatives. In the past OPC engineers have been pushing for more and more design constraints in order to allow the OPC flow to be successful. The PW-OPC approach is more adaptive compared with traditional single focal plane OPC, and can still converge to an acceptable solution in complicated (unforeseen) layout configurations, without the need to introduce complicated design constraints.