Advanced salicides for 0.10 μm CMOS: Co salicide processes with low diode leakage and Ti salicide processes with direct formation of low resistivity C54 TiSi2

Abstract The scaling of CMOS technologies to 0.10 μm and beyond imposes increasingly demanding constraints to self-aligned silicide (salicide) processes. For high performance devices, it is essential that salicide processes achieve low gate and source-drain sheet resistance as well as low silicide to source-drain diffusion contact resistance, and maintain low junction leakage. This becomes increasingly difficult as junction depths and linewidths are scaled. In this paper we present an overview of the development of advanced Ti and Co salicide processes, with implementations into a high performance 0.10 μm complementary metal-oxide-semiconductor (CMOS) technology. For Co salicide, the main scaling issue is diode leakage on shallow junctions. We show that the use of pre-amorphization implants or a pre-Co deposition sputter etch improves diode leakage distributions, but fails to eliminate high leakage outliers. Co deposition temperature and rapid thermal processing (RTP) variables were found to have a strong effect on diode leakage, with optimization of either one resulting in tight low leakage distributions on shallow junctions. For conventional Ti salicide processes, the main scaling issue is sheet resistance on narrow lines due to incomplete high resistivity C49 TiSi 2 to low resistivity C54 TiSi 2 transformation. We present X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM) studies that indicate that direct growth of C54 TiSi 2 bypassing the C49 phase is achieved at low temperatures on polycrystalline or amorphous Si with the addition of Mo impurities, eliminating the narrow line effect. The mechanism is demonstrated to be nucleation of MoSi 2 and an unidentified phase at the Ti/Si interface, followed by epitaxial growth of C54 TiSi 2 on these templates. Ti salicide processes with Mo impurities were evaluated, demonstrating an optimized one-step RTP process combining Mo and pre-amorphization implants that maintains low sheet resistance to 0.06 μm gate lengths. Successful implementations into a 0.10 μm flow were achieved both for optimized Co salicide or Ti salicide processes.