An energy-efficient sample-and-hold circuit in CNTFET technology for high-speed applications

In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both the input sampling and output buffer switches. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters. The simulation results confirm that the proposed S/H circuit properly operates for the data rates of higher than 2 GS/s. In addition, the proposed S/H circuit shows 14-bit resolution, 86.29 dB of SNDR for a 0.4 Vp-p, 218.75 MHz sinusoidal input signal at 2 GS/s sampling rate.