A well-synchronized sensing/equalizing method for sub-1.0 V operating advanced DRAMs

In standard DRAMs, a half-V/sub cc/ bit-line (BL) precharging method is widely used because of its several advantages. However this method faces several problems as the power supply voltage Vcc becomes lower. This paper describes such problems as the MOS transistors in the sensing/equalizing circuits are affected by the body effect, fluctuation of channel length (L), and leak current. It is thefefore difficult to decide the value of the V/sub th/ which satisfies the above conditions. Accordingly, we propose a well-synchronized sensing/equalizing method that enables an ultra low-voltage operation and makes determining the V/sub th/ easy.