Approximate data reuse-based processor: a case study on image compression

In most embedded systems, how to design accelerators of end applications under stringent design constraints has been a crucial issue. In this paper, we employ a new computation paradigm "approximate computing" to resolve this issue. More specifically, our work focuses on and reuses computations which have recently produced results that are expected to be similar enough to the current ones - "approximate data reuse." This concept enables to reduce computations by skipping instructions. We develop accelerator designs with this concept holistically from both hardware (architecture) and software (compilation) to achieve sufficient speedup and energy saving while mitigating the area overhead at the cost of some error. This paper provides mainly three contributions: architectural extensions applicable to a variety of processors even under a stringent constraint on circuit area, parameterization of important features of our method so that the degree of approximate data reuse can be easily tuned for different applications, and exhaustive evaluations on combinations of key parameters through our case study. A case study was quantitatively conducted using a realistic application (image compression) to demonstrate the effectiveness of our method over conventional ones.