A 3-D WASP module for real-time signal and data processing

Progress to data has concentrated on the integration of 8192 processors on a single silicon wafer (viz., a 2-D WASP (Wafer Scale Integration Associative String Processor) device). The author considers the migration of the design concept to 3-D WASP wafer stacks. A 3-D WASP architecture is described and compared with its 2-D WASP predecessor. Benefits in size, weight, power, reliability, and cost are discussed, and cost-effectiveness figures-of-merit on the order of 100 tera-OPS/ft/sup 3/, 100 tera-OPS/lb, 1 giga-OPS/W, and 10 mega-OPS/$ are forecast. >