A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications

Designing embedded systems efficiently has always been of significant interest. This has tremendously scaled-up for contemporary applications with their increasing complexity and the need to satisfy multiple conflicting constraints. This paper presents a high-speed Hardware Software Partitioning (HSP) technique for the design of such systems. The Partitioning problem has been modeled as a multi-dimensional optimization problem with the aim of minimizing the area utilization, power dissipation, time of execution and system memory requirement of the implementation. A two-phased algorithm has been proposed which also takes into consideration the communication costs between hardware and software Processing-Engines (PEs) while partitioning. Detailed empirical analysis of the proposed algorithm is presented to ascertain its efficiency, quality and speed.