Implementation of low power one bit full adder with cadence tool

Abstract In this research paper, the one-bit low power hybrid adder circuit is developed by additional logic of direct polarization and the reverse polarization method (FSB / RSB) of the Complementary metal-oxidesemiconductor (CMOS) and Transmission Gate Logic (TGL). A full adder of 1-bit is proposed in 180 nm technology and the performance parameters, such as delays, strengths, and areas, are compared to such as CMOS, 10 T, 14 T, and Hybrid Connectors. The design uses a power supply of 1.8 V for 180 nm technology. Compared to other existing full additive designs, there is a better improvement in the strength of the proposed adder and PDP reference.