CMOS (complementary metal-oxide-semiconductor) full adder and method thereof

The present invention discloses a CMOS full-adder and method relates to the field of integrated circuit technology, the CMOS full-adder carry output includes a series circuit and an output circuit and a standard; the carry output circuit comprising: an inverter and a parallel the circuits P1 and N1 circuit; said circuit P1 and N1 are connected to the circuit of the inverter; standard and said output circuit comprises: a circuit inverter P2 and N2 and a parallel circuit; said circuit P2 and the said circuit N2 are connected to said inverter; P2 said circuit comprising: a parallel circuit of a circuit P21 and P22; N2 said circuit comprising: a parallel circuit of a circuit N21 and N22; the present invention is to ensure that N-bit adder composed of while it is having a significant speed advantage of reducing the number of MOS transistors, reducing the load capacitance of the internal node and the input signal of the full adder unit, and can improve the operating speed of the circuit and reduces power dissipation.