A distributive serial multi-bit parallel test scheme for large capacity DRAMs

This paper describes a distributive serial multi-bit parallel test scheme suitable for large capacity DRAMs. It achieves a high parallel test bit number and, with regard to cells and sense amplifiers, the same operational margin as normal mode. Further, it imposes little restriction on test patterns. The scheme has successfully achieved a 512 bit parallel test on an experimental 256Mb DRAM.