A 1.1 V SOI CMOS frequency divider using body-inputting SCL circuit technology

SOI CMOS technology is one of the most effective candidates for realization of low power and high performance digital/RF circuits, with demand for single-chip LSI in portable communications equipment. By optimizing the threshold voltage, the CMOS logic in digital circuits can operate at less than 1 V (Fujii et al, 1999; Fuse et al, 1997). In the series gating ECL (emitter coupled logic) or SCL (source coupled logic) which is often used in RF circuits, on the other hand, the minimum operating voltage is raised to 1.8-2.6 V, due to the stacked configuration where plural transistors are connected in series (Yamashina et al., 1992). In this paper, we propose a body-inputting SCL circuit, which decreases the minimum operating voltage to around 1 V, by applying the input signal to the body of SOI devices. The fabricated 1/128 frequency divider realized 1.1 V operation with a maximum clock frequency of 450 MHz and each current source of 35 /spl mu/A.